Results from WP3 - Advanced Characterization & Reliability

Our goal is to identify specific limitations in terms of parasitic effects and reliability issues for GaN lateral power devices. Focus is on the identification of degradation mechanisms and prediction of physical models/laws , which can be used for accurate lifetime extrapolation  and qualification for GaN based power devices. 

From the lab:   

Unit Probe Yield Improvement on Baseline Activity (Depletion Mode Devices)
Improvement of yield results in higher production efficiency and reduction in manufacturing costs. High and uniform Yield also indicates a stable and reliable process flow. Over the last 9 months significant focus was devoted to improve the epitaxy/process yield and establishment of a baseline procedure. Since ON Semiconductor’s 650V Depletion Mode GaN Power Transistors were closest to maturity, establishment of the baseline procedure was started on the d-HEMT platform. Yield is calculated based on the unit probe data measured on 140 mm multi-finger power transistors. The measured data is binned as per the specification limit implied on the technology. In case, the device parameter exceeds the specification limits, it is considered as a ‘FAIL’. A few of the major parameters which are currently used for measured data comparison and binning are the Dynamic On-resistance (measured over the whole voltage range upto 650V) and off-state leakages. The current limits used for Dynamic On-resistance and off-state leakages (gate and drain) are 5% (ON: 400us ; OFF: 40 msec) for  any quiescent voltage upto 650V and 100nA (absolute value), respectively.
 Figure 1, shows a typical graph showing the evolution of Yield over the previous 9 months. As can be observed during the earlier months one of the major reasons for Yield loss was high Dynamic On-resistance followed by high off-state drain leakage. Such “Soft” failures resulted in very fluctuating Yields ranging between ~10% to >90%.  Several iterations of epitaxial and device architecture improvement was carried out, which lead to the achievement of an average (and stable) Yield figure of >90%. Dynamic On-resistance issue was significantly reduced. Work in ongoing for even further improvement to reach almost 100% Yield, which is in currently in-line with ON Semiconductor’s future quality roadmap of “Road to Zero Defects”.

Figure 1: Yield graph showing the evolution of Yield figures on ON Semiconductor’s 650V d-HEMT Technology during the previous 9 months. The Yield table consists of several Lots (and including wafers) and is based on unit probe measurement data on 140 mm multi-finger power transistors (>1600 power transistors/wafer). Several iterations of Epi and process development lead to the achievement of an average Yield figure > 90%. 


Development of Enhancement Mode Technology (p-GaN Gate)

ON Semiconductor is currently working on the development of a true Enhancement Mode (eGaN) technology based on p-type doped GaN gate architecture. Primary challenges involved in such technological development include development of a low damage and highly selective (pGaN to AlGaN barrier) p-GaN etch recipe in the access regions, achievement of positive threshold voltage, proper passivation of the access regions for suppression of off-state leakages and reduction of Dynamic On-resistance, etc. High etch selectivity of pGaN etch is typically obtained with high Al-content in the barrier, which however, tends to shift the threshold voltage more negative due to the presence of higher number of carriers in the channel because of higher polarization effects. Reduction of Al-content (/%) shifts the threshold voltage positive but reduces the etch selectivity, which leads to higher On-resistance in the access regions. Furthermore, the etch process needs to be fine-tuned in order to eliminate any plasma induced damages (PID) on the etched surfaces (pGaN sidewalls and access regions), which might result in higher Dynamic On-resistance and/or other reliability issues. 

Figure 2a: Figure showing the magnitude and distribution of On-resistance as a function of pGaN etch recipes (denoted by different color codes). The On-resistance is measured on power transistors by forcing 1A on the drain and measuring the voltage drop on the drain for an On-state gate voltage of 6V.

Figure 2b: Figure showing our global threshold voltage versus On-resistance graph for difference etch process splits. Current target is to achieve low On-resistance (<15 with threshold voltages of >1.5V.

Several etch processes with different etch chemistries, bias power, temperature, pressure etc were tested on similar epitaxial layers for comparison purposes. As can be seen in Figure 2a, both the magnitude and the distribution of the On-resistance can be significantly influenced by the choice of the etch processes and parameters and only a few of such recipes helped us to achieve our 15 On-resistance target. Figure 2b, shows our global threshold voltage versus On-resistance graph. Such a graph is obtained when the On-resistance data of Figure 2a is plotted against their corresponding threshold voltage values. As can be seen, wafers which meet our On-resistance specifications does not meet the threshold voltage requirements of >1.5V, and are mostly depletion mode devices (negative threshold voltage). One particular wafer, denoted as NH33275 (#3) received a special processing step post pGaN gate etch, which managed to shift the threshold voltage to positive magnitude. A data comparison of threshold voltages comparing different gate processes is shown in Figure 3, proving the fact that not only the barrier’s Al% but also gate module process conditions can have a major impact on the threshold voltage. 

Figure 3: Figure showing the data comparing the threshold voltages among the different gate module processing. The threshold voltage is measured at 1uA/mm for VD=1V on power transistors. Almost all the wafers are depletion mode (negative threshold voltage) except NH33275 #3 which showed a positive threshold voltage of ~0.5-1.5V with an on-wafer distribution of ~1V.